File (VHDL)
VHDL source code is contained in text files. A file can contain one or many
Design Units, i.e. entities, architectures, configurations, packages, or package
bodies.
Syntax
{A file contains one or many DesignUnits}
DesignUnit = {both}
ContextClause ...
LibraryUnit
ContextClause = {either}
Library
Use
LibraryUnit = {either}
Entity
Architecture
Configuration
Package
PackageBody
Things to remember
Library and use definitions are not global throughout a file; they must be
repeated for every entity or package.
Tips
It is best to restrict the contents of a file to one entity and the associated
architectures, one package and the associated package body, or a set of
related configurations. This makes the VHDL source files easy to manage
and avoids unnecessary re-compilation:
Put only one entity together with its architectures in the same file.
Do not put a package in the same file as an entity.
Do not put a configuration in the same file as an entity.
An alternative approach is to put each design unit in a separate file. This
minimizes re-compilation. but there are more files to manage.
See Also
Entity, Architecture, Configuration, Package, Library, Use
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